Apogee Seamless Chip Assembly


Apogee is a complete top down floor planning and chip assembly tool that complements Aprisa, ATopTech's block level implementation tool. Apogee and Aprisa's shared timing, placement, and routing engines enable excellent correlation between block and top level timing, and provide a seamless integrated design environment for complex chip designs.


  • Virtually unlimited capacity with multi-cpu capability
  • Automatic hierarchy partitioning with full rectilinear support
  • Fast, near-detail quality automatic macro placement
  • Support for a mix of black box and completed block netlists
  • Virtual top level timing optimization and block timing budgeting
  • Rapid budget-less prototyping with unique "transparent hierarchy" optimization
  • Seamless hierarchical ECO capability with unparalleled flexibility
  • Repeated block optimization
  • Database level access for manipulating netlist hierarchy within physical design environment
  • Hierarchical flow support for various advanced clock topologies including multi-point, mesh, and H-tree
  • Unique, on-the-fly timing and physical abstraction eliminates creating of extra files and models for blocks while drastically reducing run time and memory
  • Global router based congestion-aware pin optimization capable of handling complex rectilinear blocks and repeated block pin assignments
  • Automatic feedthrough insertion and feedthrough buffering
  • Supports push down of top level objects into blocks including custom routes and blockages
  • Block latency aware top level CTS
  • Block timing aware signal integrity fixing
  • Fast, top level optimization and router that correlate well with block level timing
  • Easy, intuitive use model for merging block projects and switching between different block views