New place-and-route architecture provides > 2X faster design closure times with better quality of results than conventional tools
Santa Clara, CA – October 3, 2018 — With semiconductor technology moving at a rapid pace to advanced process nodes, Avatar Integrated Systems, a leading provider of physical design implementation solutions, has introduced new architecture to its Aprisa and Apogee solutions. The new release provides a breakthrough detailed-route-centric place-and-route architecture addressing the challenges facing designs at 16nm and below process nodes.
"Advanced place-and-route technology is important for our silicon design activities as we move to more advanced processes," said Freddy Gabbay, vice president of chip design at Mellanox Technologies. "The detailed-route-centric technology introduced with the new release of Aprisa consistently delivered better quality-of-results and predictable DRC and more than two times faster design time."
As designs move to sub-16nm, wire and via resistance become the dominant factor for the performance of the designs. Interconnect delay and other wiring related effects can no longer be handled without close involvement of detailed routing. This makes it critical to have the precise detail routing prediction readily and efficiently throughout the place-and-route (P&R) flow. These predictions include routing layers, routing patterns, routing congestion, pin congestion, IR/EM effects, in addition to traditional process design rules.
Conventional placement-centric place and route architecture methodologies with separate sequential flows are no longer adequate for 16nm and below designs. They cause significant pre-route versus post-route timing correlation issues, excessive design iterations, and suboptimal quality-of-results. The introduction of the detailed-route-centric architecture in Aprisa and Apogee uses unified runtime data-model throughout the entire flow. This unique architecture facilitates efficient and frequent communication between placement optimization, CTS optimization and detailed routing. The detailed route information is always consistent and up-to-date throughout the flow, which helps deliver improved quality-of-results, reduces iterations and speeds design convergence more than 2X faster than competition.
"eSilicon has used Aprisa on several very large and complex FinFET chips across several process nodes, including 16nm and 14nm," said Sid Allman, vice president, design engineering at eSilicon. "We have successfully used Aprisa at both the block and top level with very good results. We expect to apply the new release to our advanced 7nm work as well."
In addition to the detailed-route-centric place and route architecture, the new release also includes:
• Full support of 7nm technology
• IR-aware P&R for IR-hotspot avoidance
• Automatic EM violation avoidance and fixing
• Native support of Path-based analysis in P&R optimization, reduce design pessimism and improve power by up to 20%
"We are committed to developing new breakthrough technologies to address the most challenging designs in the industry," said Dr. Ping-San Tzeng, chief technology officer at Avatar Integrated Systems. "This breakthrough architecture to our flagship products provides leading design teams with much faster design closure while improving the quality of results at 16nm and below."
Avatar will be highlighting Aprisa and Apogee's new architecture at the upcoming TSMC OIP Symposium, October 3, 2018 at the Santa Clara Convention Center in booth #803 and at Arm Techcon, October 16 – 18, 2018 at the San Jose Convention Center in booth #827.
Aprisa is a complete place-and-route (P&R) engine, including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common "analysis engines," such as RC extraction, DRC engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
Apogee is a full-featured, top-level physical implementation tool that includes prototyping, floor planning, and chip assembly. The unified hierarchical database enables a much more streamlined hierarchical design flow. Unique in-hierarchy-optimization (iHO) technology helps to close top-level timing during chip assembly through simultaneous optimization at top level and at blocks, reducing the turnaround time for top-level timing closure from weeks to days.
About Avatar Integrated Systems
Avatar Integrated Systems is a leading software company in the Electronic Design Automation (EDA) industry focused on Physical Design Implementation. The company's products enable integrated circuit (IC) designers to create semiconductor chips which enable today's electronic devices, such as smartphones, computers, internet equipment, IoT wearables, etc. Avatar's products are built on the proven technologies acquired from ATopTech, Inc. Avatar Integrated Systems is headquartered in Santa Clara, Calif. with subsidiaries and offices in Taiwan, India, Japan, and Korea. The company continues to serve global customers with cutting-edge digital place and route technology and closely partners with customers to reach their design successes. For more information visit: www.avatar-da.com.
Aprisa and Apogee are registered trademark of Avatar Integrated Systems. Any other trademarks or trade names mentioned are the property of their respective owners.