Thu, Apr 30th, 2020 — DeepChip

Avatar Aprisa benchmarks vs. Innovus/ICC2 at 7nm is Best of 2019

AVATAR MAKES 7NM: Last year's "Best of 2018" report got a lot feedback from engineers who were happy to see Avatar back in the game. This year users shared that Avatar has since crossed that hurdle and is 100% functional and WORKING at 7 nm.

Thu, Jan 31st, 2019 — Semi Engineering

EDA Grabs Bigger Slice Of Chip Market

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019.

With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved.

Wed, Jan 23rd, 2019 — Deep Chip

Avatar Big Comeback in Digital P&R #4 Best of DAC 2018

CHOICE IS GOOD: A whole bunch of digital PnR users were quite happy to see that AtopTech ... err... correction ... make that "Avatar" was back in the EDA game.

Mon, Oct 29th, 2018 — Semi Engineering

The Impact of Moores Law Ending

Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.

Mon, Oct 8th, 2018 — Electronics Weekly UK

Avatar adds architecture for sub-16nm nodes

As designs move to sub-16nm, wire and via resistance become the dominant factor for the performance of the designs. Interconnect delay and other wiring related effects can no longer be handled without close involvement of detailed routing.

Wed, Oct 3rd, 2018 — Deep Chip/ Cooley

DeepChip: Avatar at TSMC OIP Questions

My spies reported Avatar (Atoptech) was launching its own REV2 remake of their Aprisa PnR tool at TSMC OIP in Santa Clara on Wednesday (today). Word is both Mellanox and eSilicon will be speaking up for this Aprisa REV2
but it's not know whether they'll be in the Avatar TSMC OIP booth or not.

Tue, Sep 25th, 2018 — SemiWiki

Apogee Pipelining in Real Time

Anatomy of pipelining
Pipeline involves the use of flip-flop and repeater insertion --although some designers tend to focus on flip-flop insertion part, as it is assumed that the implementation tools are to perform repeater insertion by default (such as during synthesis stage or placement/route optimization).

Thu, Jul 26th, 2018 — Semi Wiki

Aprisa & Apogee: The New Avatars

Earlier physical optimization impacts a design QoR gain and can disclose potential hurdles in dealing with unknown design variants such as new IP inclusion or new process node issues. Along the RTL-to-GDS2 implementation continuum, a left-shift move requires a robust modeling and proper context captures in order to produce meaningful outcomes.

Fri, Jun 29th, 2018 — EE Times

EDA Start-up Rises From the Ashes of ATopTech

SAN FRANCISCO — A startup, formed from the auctioned assets of ATopTech, showed up at the Design Automation Conference (DAC) here this week open for business and with two well-respected EDA veterans newly added to its leadership team.

Avatar Integrated Systems features substantially all of the technology of ATopTech, including the popular Aprisa and Apogee place-and-route tools used by a number of chip companies. The company also features most of the former employees of ATopTech — including ATopTech co-founder and chief architect Ping San Tzeng — as well as former Cadence Design Systems executives Chi-Ping Hsu and Charlie Huang.

Tue, Jun 26th, 2018 — Electronics Weekly

Avatar planning tools are based around unified hierarchical database

The tools are built on ATopTech technologies which were the subject of a lawsuit brought by Synopsys. Following that, the tools were rebuilt, the command which had been the same as the Synopsys command was changed, explained Lily Cheng, manager of applications engineering, Avatar.